Very large scale integration (VLSI) integrated circuits and other types of electronic circuits commonly include circuits for performing the comparison of two or more signals. The latter circuits are referred to herein as comparator circuits or simply comparators, and may be implemented in the analog domain or the digital domain.
In the analog domain, two fundamental comparators are the analog sense amplifier and the differential amplifier. The differential amplifier is also referred to as an operational amplifier or simply op-amp. These analog comparator circuits typically resolve the difference between two signals that are complements of one another, where in this context the complement of one of the two signals may be defined as the other signal mirrored around a common mode signal.
FIG. 1 illustrates the concept of complementary signals in the analog domain. As shown in the figure, a common-mode input voltage VCM is the arithmetic mean of two signals VA and VB, and is defined as (VA+VB)/2. Since signals VA and VB are equally displaced above and below the common mode voltage VCM by an amount Δ, these two signals are the analog complements of one another. The separation of VA and VB is known as the differential-mode input voltage and is given by VD=(VA−VB)=2Δ. The two input signals can thus be represented as a common-mode component and a differential-mode component. When the magnitude of Δ is small, these analog comparator circuits perform amplification and can therefore be used to sense very small voltage differences.
FIGS. 2A and 2B show examples of conventional differential amplifiers. The voltage supplies for these and other circuits described herein are illustratively Vdd and ground, but other supplies could of course be used. For example, Vss voltage supply values other than ground could be used.
A differential amplifier is an analog amplifier that has the capability of extracting a signal with respect to another signal. The other signal can be a common-mode value or its complement. Referring to FIG. 2A, the differential amplifier receives two balanced inputs VA and VB. The generation of the signals Vnch and Vpch follows conventional rules. In the differential amplifier of FIG. 2B, the two input signals are the signal VA and the common mode voltage VCM. Both of these differential amplifiers compare the difference between their two input signals and generate one or more outputs. More particularly, the FIG. 2A differential amplifier generates an output signal out and its complement out, and the FIG. 2B differential amplifier generates the complement output signal out.
FIGS. 3A and 3B show examples of conventional sense amplifiers. Each of the sense amplifiers includes transistors m1, m2, m3, m4, m5 and m6 arranged as shown. It should be noted that for simplicity of illustration transistor designations m1, m2, m3, etc. will be reused herein to designate different transistors in different circuits. These designations should therefore not be construed as denoting common elements in all figures.
The transistors m1 and m2 in the circuits of FIGS. 3A and 3B form a cross-coupled portion that provides positive feedback during an evaluation operation of the sense amplifier. When an input clock signal ck applied to the gates of m3 and m4 is high, the circuit is initialized and m3 equalizes the potential at the output nodes. In FIG. 3A, an input signal VA and its complement VB are each applied to one of the evaluation “legs” of the sense amplifier which in this example correspond to transistors m5 and m6, respectively. The evaluation legs are also referred to herein as input legs. In FIG. 3B, the input signal VA is compared against the common mode voltage VCM.
Both the FIG. 3A and FIG. 3B circuits are evaluated when the clock signal ck goes low. Note that for a small differential-mode signal, both evaluation legs, i.e., the left leg (m5) and the right leg (m6), can be enabled. This will prevent the output nodes from achieving full digital values and will cause additional power dissipation.
In the digital domain, sense amplifiers can be used to perform comparisons between two digital Boolean functions that are complements of one another. A trivial case is when a Boolean function and its inverse are compared. For example, assume input signal VB is the Boolean complement of input signal VA. Note that if VA=0, VB=1 and vice versa. The sense amplifier circuits given in FIGS. 3A and 3B can therefore be used to extract the digital signal in this case. In FIG. 3B, the value of VCM would be between a 0 and a 1, i.e., Vdd/2.
FIGS. 4A and 4B show sense amplifiers suitable for performing comparisons in a case when the Boolean function has more than one value. In this case, a complementary function F is formed by applying the well-known DeMorgan rule to a Boolean function F. For instance, if F=AB, then F=A+B, in accordance with the DeMorgan rule. The sense amplifier of FIG. 4A implements these two Boolean functions. The left input leg circuit structure for F=AB corresponds to the series combination of m5 and m6. The corresponding result is found on the opposite side of the circuit. Similarly, the right input leg circuit structure for F=A+B corresponds to the parallel combination of m7 and m8. Note that the inputs that are applied to this circuit must be complementary. For example, if A=1 and B=0, then A=0 and B=1. More particularly, in all four exhaustive combinations of the inputs A and B in this example, the inputs applied to one side of the circuit are the binary complement of those inputs applied to the other side. Thus, only one leg of the circuit is enabled at a particular time.
Transistors m1, m2, m3 and m4 in the circuits of FIGS. 4A and 4B are configured as in the circuits of FIGS. 3A and 3B. As noted above, the left input leg of each of the circuits in FIGS. 4A and 4B is comprised of transistors m5 and m6, each associated with a corresponding one of the inputs A and B, and the right input leg of each of the circuits is comprised of transistors m7 and m8. Note that transistors in parallel in the right leg translate to a series connection in the left leg, and vice versa, as a consequence of the DeMorgan rule. Also, note the inversion of the inputs from one side of the circuit to the other. Thus, the actual structure or connectivity of each side of the circuit is related to that of the other side through the DeMorgan rule. As a result, in order to operate the circuit, the inputs that are applied to each side must be complementary, as previously indicated. The structure of the transistor connectivity requires this relationship between the inputs.
The circuits of FIGS. 4A and 4B operate in substantially the same manner as the corresponding circuits of FIGS. 3A and 3B. However, since the inputs to transistors m5-m8 in the circuit of FIG. 4A are digital and follow the DeMorgan rule, one of the two evaluation legs, i.e., the left leg comprising m5 and m6 or the right leg comprising m7 and m8, will be fully enabled while the other will be fully disabled. This allows the output nodes to achieve full digital values and reduces the power dissipation of the circuits after evaluation.
The common mode technique can be applied to more complex Boolean functions, but generally becomes more difficult to predict as the function becomes more complex and the number of inputs increases. With reference to FIG. 4B, the gates of the devices in the right leg of the sense amplifier have the common mode voltage VCM applied to them. The widths of transistors m5 and m6 relative to the widths of transistors m7 and m8 can potentially cause this circuit to fail. However, by appropriately sizing the width of the transistors in the right leg to be less than that of the left leg, the circuit can be made to operate properly. Although not shown as such in the figure, a single device may be used to implement the two parallel transistors m7 and m8. Furthermore, the voltage applied to this single device can be Vdd instead of Vdd/2, although the width would need to be further decreased. The value of this voltage is constant at all times and of course the same for every evaluation.
Note the difference in the meaning of complementary signals in the digital and analog domains. In the digital domain, the two sets of inputs have a discrete number of input possibilities given by 2n, where n is the number of inputs in a given leg. For example, the inputs to the left leg the FIG. 4A circuit can be 00, 01, 10 or 11. In the analog case described in conjunction with FIG. 3A, the two inputs can have continuous values of Δ around the common mode voltage. In the special case of Δ=Vdd/2 the analog sense amplifier operates as a digital sense amplifier.
In the above-described conventional analog comparators, at most only two analog inputs are compared at once. U.S. Pat. No. 6,191,623, issued Feb. 20, 2001 in the name of inventor T. J. Gabara and entitled “Multi-Input Comparator,” and U.S. patent application Ser. No. 09/162,852, filed Sep. 29, 1998 in the name of inventors T. J. Gabara and S. A. Mujtaba and entitled “Multi-Input Comparator,” both of which are incorporated by reference herein, describe comparator circuits having more than two inputs.
FIGS. 5A, 5B and 5C show example gate structures having complementary input structures. Referring to FIG. 5A, upper and lower transistor arrays comprising pairs of transistors m7, m8 and m5, m6, respectively, are formed using n-channel devices. Note that the complementary transistor array legs have opposite connectivity structures in that if one leg has parallel transistors, the other leg has its corresponding transistors arranged in series. Because of the use of complementary input structures, the inputs to the upper leg in FIG. 5A need to be inverted. FIG. 5B shows the FIG. 5A circuit configured with inverters to generate the inputs to the upper leg. The inverters and n-channel devices can be replaced with p-channel devices, resulting in the circuit of FIG. 5C. In each of the circuits of FIGS. 5A, 5B and 5C, an output F is generated at the output of an inverter as shown. The FIG. 5C circuit is an example of a CMOS AND gate, and adheres to the complementary transistor structure previously described. There is thus a simple one-to-one correspondence between the left and right legs of a sense amplifier as described in conjunction with FIG. 4A and respective top and bottom legs of the related static gate structure shown in FIG. 5C.
FIGS. 6A, 6B and 6C show additional examples of gate structures with complementary inputs. The circuit shown in FIG. 6A is a CMOS OR gate, comprised of transistors m5, m6, m7 and m8 and an inverter, in which inputs A and B each drive the capacitance of two gates. FIG. 6B shows the circuit that results if the two upper series p-channel transistors m7 and m8 driven by the A and B inputs are replaced by a single p-channel transistor m7 having its gate connected to ground. This circuit is analogous in certain ways to the circuit of FIG. 4B. As noted previously, instead of using the common mode voltage as in FIG. 4B, the applied voltage in this case can be Vdd. However, since m7 in FIG. 6B is a p-channel transistor, the applied voltage must be opposite in polarity, or Vss. Since this voltage is a constant at all times, the FIG. 4B and FIG. 6B circuits exhibit equivalent behavior.
By properly sizing of transistors, the FIG. 6B circuit can be configured to perform digital operations. This gate structure is known as a pseudo-NMOS gate and provides advantages in terms of increased throughput speed. However, the circuit can exhibit excessive power dissipation in that if either A or B is high, a resistive path forms between Vdd and ground. In this gate structure, a single upper device that is always enabled (m7 in FIG. 6B) replaces the complementary structure (m7 and m8 in FIG. 6A). Although the upper device is not being driven by either input signal A or B, its ground potential input is analogous to a common mode signal since its voltage is always constant.
FIG. 6C shows a modified circuit having a reduced power dissipation but substantially the same speed advantages of the FIG. 6B circuit. In the FIG. 6C circuit, a clock signal ck is used to enable each leg in alternate cycles. That is, when ck is low, the upper leg is enabled due to m7 which precharges node fout, while the lower leg is disabled due to the series transistor m1. When ck is high, the upper leg is disabled and the lower leg can be conditionally enabled depending on the values of A or B either pulling the node fout low or leaving it unaltered. Thus in this circuit, one can never have the situation where both legs are simultaneously enabled. The ck signal which is applied to both legs ensures this condition. When the circuit is evaluated, ck is high and during this time interval the voltage applied to m7 is a constant or Vdd. The FIG. 6C circuit, known as domino CMOS, is equivalent to the common mode circuit of FIG. 6B since the voltage applied to the m7 leg remains constant during evaluation.
Note that the common mode signal in the circuits of FIGS. 6B and 6C is essentially a constant during evaluation. The final Boolean result ultimately depends on the value of the input Boolean variables and not on the condition of the common mode leg. In other words, the common mode determines the balance point of the circuit but the final output is a function of the input variables.
FIGS. 7A, 7B and 7C illustrate digital comparator circuits of a type described in U.S. Pat. No. 4,767,949 issued Aug. 30, 1988 in the name of inventor W. T. Mayweather, III and entitled “Multibit Digital Threshold Comparator,” which is incorporated by reference herein. The FIG. 7A circuit includes transistors m1-m10 and an inverter arranged as shown. The circuit as shown in FIG. 7A may appear to have non-complementary input structures in that the DeMorgan rule does not seem to be followed between top and bottom legs of the circuit. However, a decomposition of the FIG. 7A circuit as shown in FIGS. 7B and 7C illustrates that the input structures in the FIG. 7A circuit are in fact complementary.
FIG. 7B copies only the lower leg n-channels and forms the complementary upper leg circuit using the DeMorgan rule. That is, the series connection of m3 to the parallel combination of m1 and m2 is translated as m4 being in parallel with the series combination of m9 and m10. Finally, the parallel leg comprising the series combination of m7 and m8 translates into the series path comprising the parallel combination of m5 and m6.
Transistors m5 and m6 of FIG. 7B are then duplicated as respective transistor pairs m5, m5a and m6, m6a, and the line denoted “wire” in FIG. 7B is cut as shown in FIG. 7C. This wire can be cut because each path contains the influence of the signals X and Y. The path consisting of transistors m5a, m6a, m9 and m10 can be further simplified by removing transistors m5a and m6a since they are redundant. This simplification results in the circuit as shown in FIG. 7A, thereby confirming that this circuit in fact has complementary input structures.
As is apparent from the foregoing, conventional comparator circuits have complementary input structures configured for processing of complementary inputs. A need exists in the art for improvements in comparator circuits in terms of reduced power dissipation, transistor count and throughput delay relative to the conventional circuits.